Multipliers are a major energy and delay contributor in modern compute-intensive applications due to their complex logic architecture. As such, designing multipliers with reduced energy and faster speed has remained a thoroughgoing challenge. This paper presents a novel, carry-free multiplier, which is suitable for a new-generation of energy-constrained applications. The multiplier circuit consists of an array of memristor-transistor cells that can be selected (i.e., turned ON or OFF) using a combination of DC bias voltages based on the operand values. When a cell is selected it contributes to

In this paper, an enhanced version of the improved Howland circuit is proposed. An improvement in output impedance to a maximum factor of two is obtained. The theoretical derivation is presented, including analysis from a two-port network perspective, and both simulation and experimental results using a general purpose opamp confirm the expected result. © 2019 John Wiley & Sons, Ltd.

A power-law compensator scheme for achieving robust frequency compensation in control systems including plants with an uncertain pole, is introduced in this work. This is achieved through an appropriate selection of the compensator parameters, which guarantee that the Nyquist diagram of the open-loop system compensator-plant crosses a fixed point independent of the plant pole variations. The implementation of the fractional-order compensator is performed through the utilization of a curve-fitting-based technique and the derived rational integer-order transfer function is realized on a Field

In this paper, we present a quadrature-phase oscillator that can provide four output voltages while operating from a single 0.5 V supply. The oscillator is based on two cross-coupled modified differential pair cells and provides signals with a phase difference of ±180° or ±90° depending on the chosen output nodes. A test chip with an active area of 0.175 mm2 was designed and fabricated in a 65-nm CMOS process and its measurement results show a phase noise of −119.5 dBc/Hz at 1 MHz offset from a carrier frequency of 1.967 GHz while consuming 6.15mW. Finally, experimental results show a FoM of

The porous nature of the electrode material in supercapacitors and the apparent conductivity of the electrolyte cause their impedance to show a complex frequency-dependent behavior, which in turn makes it incorrect to treat them as ideal capacitors, even at a frequency of a few millihertz. This is particularly crucial if the intended application requires a configuration that uses stacked supercapacitor banks, in which errors in defining the metrics of the individual components accumulate. Although manufacturers provide supercapacitor ratings under DC only, by using a detailed impedance

Concentrated Solar Power (CSP) systems have a good potential as a renewable energy candidate that are based on converting the incident solar thermal energy to an electrical energy. In this paper, CSP using spot Fresnel lens instead of traditional lenses is presented to enhance the efficiency of the system, where Silicon Carbide (SiC) is used as a coating material for the receiver of the system due to its high thermal conductivity. The presented prototype has been investigated for uncoated spot Fresnel lens CSP, and for spot Fresnel lens CSP with the SiC as a coating material showing the

In this paper, a new realization of the fractional capacitor (FC) using passive symmetric networks is proposed. A general analysis of the symmetric network that is independent of the internal impedance composition is introduced. Three different internal impedances are utilized in the network to realize the required response of the FC. These three cases are based on either a series RC circuit, integer Cole-impedance circuit, or both. The network size and the values of the passive elements are optimized using the minimax and least m th optimization techniques. The proposed realizations are

Multilevel electronic systems offer the reduction of implementation’ complexity, power consumption, and area. Ternary system is a very promising system where more information is represented in the same number of digits compared to the binary systems. In this paper, ternary logic gates and some of their ternary circuit applications are presented using memristors and CNTFET inverter. This integration between memristors and CNTFET offers low static power, small area and high performance. The proposed circuits do not require refreshment like the previously published circuits and are not initial

The approximations of fractional-order differentiator/integrator transfer functions are currently performed using integer-order rational functions, which are in general implemented through appropriate multi-feedback topologies. The spreading in the values of time-constants and scaling factors, needed to implement these topologies, increases as the order of the differentiator/integrator and/or the order of the approximation increases. This leads to non-practical values of capacitances and resistances/transconductances in the implementation. A solution to overcome this obstacle is introduced in

Fractional-order lead/lag compensator realizations, using Operational Transconductance Amplifiers as active blocks, are presented in this paper. Two different types of fractional-order transfer functions, derived from the integer-order lead/lag compensator transfer function, are used to describe the behavior of the fractional-order compensator. Both types are approximated using the Padé approximation tool, and are expressed by the same form of rational integer-order transfer function. This means that both types can be implemented using the same active core, which is an important advantage from